The present invention relates to DC to DC converters, and in particular, to multi-phase converters which produce a DC output voltage at the common output of a plurality of coupled switching power supplies, for example, a plurality of buck converters.
Multi-phase converters are known. In a typical multi-phase converter, for example, a multi-phase buck converter, a plurality of buck converters are provided each having their output inductors coupled to the output node. In a typical application, each buck converter is controlled by a control circuit and may be operated such that a control switch of each buck converter switching stage is turned on at a different time than the other phases. In this way, each phase sequentially provides power to the load, reducing ripple and reducing the size of the output capacitance.
FIG. 1 shows an example of a six-phase multi-phase converter which employs the IR3500 control integrated circuit 10 and a plurality, in the six-phase case shown, six IR3505 phase ICs 30 which are controlled by the control IC. Each phase IC 30 is identical and has outputs connected to a respective buck converter comprising two switches, an upper switch Q1 functioning as the control switch and the lower switch Q2 functioning as a synchronous switch. The switch node Vs 1-6 of each respective phase is connected to an output inductor L1 through L6 for each of the phases which are connected at a common node VC and coupled to an output node VOUT through any distribution impedance present. An output capacitor COUT is coupled across the output to filter the switched output voltage.
In the typical multi-phase converter, each control switch Q1 is turned on to provide output current to charge the output inductor to provide current to the load at a time determined by a clock pulse which may be provided by the control IC. Thus, the control switch will turn on only when a clock pulse has occurred. The clock pulses for each phase IC (labeled PHSIN) are shown in FIG. 3. As shown, the PHSIN signals (IC1 PHSIN, IC2 PHSIN, IC3 PHSIN, IC4 PHSIN are each delayed to turn on the respective phase control switches Q1 out of phase from each other. The turn-on of the synchronous switches Q2 are likewise delayed, but turn on in complementary manner to the control switches.
With reference to FIG. 2 which shows in greater detail the circuit of FIG. 1, although showing only two phase ICs 30, the clock pulse is provided at CLKOUT from the control IC 10. As shown in FIG. 4, at A, and with reference to FIG. 2, when a clock pulse occurs, this starts a ramp signal PWMRMP which is shown at the non-inverting input of the PWM comparator 45 in FIG. 2. It also turns on the control switch Q1. See C of FIG. 4. PWMRMP is shown in waveform B of FIG. 4. The base level for the PWM ramp is a signal VDAC1 which is provided by the control IC 10 based on a reference voltage level set by VID signals VID0 for VID7. See FIG. 1. When PWMRMP equals the output of an error amplifier 20 in the control chip 10, which compares feedback FB from the output voltage of the converter against the reference voltage VDAC, as shown in FIG. 2, the control or high side switch Q1 is turned off and the low or synchronous switch Q2 is turned on. See waveforms C and D of FIG. 4. As shown, the control or high side switch Q1 is turned on when the clock pulse occurs and turned off when the ramp voltage equals the error amplifier output. This is shown for a range of error amplifier signals in FIG. 4B. As shown, when the error amplifier output increases due to a load step-up as shown at I in FIG. 4B, the control switch Q1 is only turned on when the clock pulse occurs and is turned off when the PWM ramp voltage has reached the error amplifier output EAIN. A shown in FIG. 4, the increased error amplifier output results in increased Q1 duty cycle. The duty cycle accordingly follows the error amplifier signal and once the error amplifier decreases due to for example, a load decrease, the duty cycle is reduced, as shown in FIG. 4C.
Accordingly, as can be understood from the above, the control switch is only turned on when the clock pulse occurs. Thus there is a delay time until the clock pulse occurs before the converter can respond to the load transient. Thus, for example, if a load transient occurs in advance of the clock pulse as shown by the dotted line at I in FIG. 4B, the converter cannot respond by turning on the control switch until the clock pulse occurs.
This is exacerbated by a situation where a large load transient occurs and the turn-on of the next-phase control switch Q1 may be inadequate to address the current requirements caused by the load transient.
Accordingly, it would be desirable to be able to provide a multi-phase converter which is capable of an immediate response to a load transient and which does not need to wait until the clock pulse occurs in order to turn on at least one of the converter control switches, and preferably all the phase control switches.